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CXD2508AQ/AR
CD Digital Signal Processor For the availability of this product, please contact the sales office.
Description The CXD2508AQ/AR is a digital signal processor for CD players and is equipped with built-in digital filters, no-sound data detection circuit, and 1-bit DAC. Features DSP block * Digital PLL * EFM frame sync protection * SEC strategy-based error correction * Subcode demodulation, CRC checking * Digital spindle servo * Servo auto sequencer * Asymmetry compensation circuit * Digital audio interface output * 16K RAM * Double-speed playback capability * New microcomputer interface circuit Digital filter, DAC block * Double-speed playback capability * Digital de-emphasis * Digital attenuation * No-sound data detection circuit * 4 Fs oversampling filter * Secondary noise shaper * PWM-system pulse conversion output CXD2508AQ 80 pin QFP (Plastic) CXD2508AQ 80 pin QFP (Plastic)
CXD2508AQ 80 pin QFP (Plastic)
CXD2508AR 80 pin LQFP (Plastic)
Applications CD players Structure Silicon gate CMOS IC Absolute Maximum Ratings -0.3 to 7.0 V * Supply voltage VDD * Input voltage VI -0.3 to 7.0 V * Input voltage VIN Vss-0.3V (min.) VDD+0.3 (max.) V * Output voltage VO -0.3 to 7.0 V * Storage temperature Tstg -40 to 125 C * Supply voltage variation VSS-AVSS -0.3V (min.) +0.3V (max.) VDD-AVDD -0.3V (min.) +0.3V (max.)
Recommended Operating Conditions * Supply voltage VDD Note) 4.5 to 5.5V (double-speed playback) 3.5 to 5.5V (normal-speed playback) 3.4 to 5.5V (low power consumption or special playback mode) * Operating temperature Topr -20 (min.) 75 (max.) C Note) VDD (min.) is varied by the playback speed and built-in VCO in the CXD2508AQ/AR. 4.5V is the value using the VCO which generates the slower frequency in doublespeed playback. The table below shows the VDD (min.) for each condition. VDD (min.) [V] Playback speed x2 x1 x 1 VCO VCO DAC block high-speed normal-speed 3.40 3.40 3.40 4.50 3.50 3.40 3.40 3.40 3.40
When the internal operation of the LSI is set to doublespeed mode and the crystal oscillation frequency is halved, normal-speed playback results.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E94602A54-ST
CXD2508AQ/AR
Pin Configuration
EMPHI PCMDI WFCK EMPH DOUT XROF C2PO MNT0 MNT1 MNT3 RFCK XPCK XUGF GTOP PCMD LRCKI FSTT C4M BCKI Vss GFS BCK LRCK WDCK
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 CXD2508AQ 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 ASYE ASYO ASYI BIAS RF AVDD1 CLTV AVss1 VDD PCO FILI FILO TEST LOCK MDS MDP
ZEROL ZEROR DTS1 VDD NLPWM LPWM AVDD2 AVDD3 XTAI XTAO AVss3 AVss2 NRPWM RPWM DTS2 DTS3
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
SQSO
SCOR
SQCK
MUTE
PCMDI
SPOC
SBSO
SPOA
SPOB
DATO
EXCK
SENS
CLOK
CLKO
EMPH
DOUT
XROF
C2PO
FSTT
MNT0
MNT1
MNT3
RFCK
XPCK
XUGF
GTOP
C4M
BCKI
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 EMPHI WFCK ZEROL ZEROR DTS1 VDD NLPWM LPWM AVDD2 AVDD3 XTAI XTAO AVss3 AVss2 NRPWM RPWM DTS2 DTS3 SCOR SBSO 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 CXD2508AR 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 9 10 11 12 13 14 15 16 17 18 19 20 LRCK WDCK ASYE ASYO ASYI BIAS RF AVdd1 CLTV AVss1 Vdd PCO FILI FILO TEST LOCK MDS MDP MON FOK
1
2
3
4
5
6
7
8
Vss
GFS
BCK
PCMD
SQSO
SQCK
MUTE
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SPOC
SPOA
SPOB
DATO
EXCK
SENS
CLOK
CLKO
XLON
XRST
DATA
XLTO
XLAT
XTSL
CNIN
SEIN
Vss
LRCKI
XLON
XRST
DATA
XLTO
XLAT
XTSL
CNIN
SEIN
MON
FOK
Vss
CXD2508AQ/AR
Block Diagram
XTAI XTAO ZEROL
66
73 74
65
ZEROR
EMPHI 63 LRCKI 43 PCMDI 45 BCKI 47 MUTE 6 BCK 46 PCMD 44 LRCK 42 WDCK 41 D/A Interface digital OUT Digital Filter + 1bit DAC
69 NLPWM 70 LPWM 78 RPWM 77 NRPWM
61 DOUT
C2PO 54 RFCK 52
55 XROF 27 LOCK digital CLV 26 MDS 25 MDP
MNT0 58 MNT1 57 MNT3 56 error corrector 16K RAM
24 MON
5 4 3 2
SQCK SQSO EXCK SBSO SCOR
WFCK 64 EMPH 62 GFS 51 XUGF 49 GTOP 48 EFM demodulator SUB code Processor
1 CPU interface
22 XLON 19 SPOA to C 11 CLOK 10 XLAT 9 7 DATA SENS
17 CLKO digital PLL asymmetry corrector Servo auto sequencer 16 XLTO 15 DATO
XTSL 18
clock generator
59
60
36
38 39 40 37
50 29 30
31 34
23
13
14
ASYO
XPCK
ASYE
CLTV
FSTT
ASYI
BIAS
FILO
PCO
C4M
FILI
RF
Note) The pin numbers are for QFP. Refer to the Pin Description for those of LQFP. -3-
CNIN
SEIN
FOK
CXD2508AQ/AR
Pin Description Pin No. R 79 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Q 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Symbol SCOR SBSO EXCK SQSO SQCK MUTE SENS XRST DATA XLAT CLOK VSS SEIN CNIN DATO XLTO CLKO SPOA SPOB SPOC XTSL XLON FOK MON MDP MDS LOCK TEST FILO FILI PCO VDD AVSS1 CLTV I I I O O O I I I I O I O O O O I O I O I/O O O I O I I O I I I I Description Outputs a high signal when either subcode sync S0 or S1 is detected. Sub P to W serial output. SBSO readout clock input. Sub Q 80-bit serial output. SQSO readout clock input. High: mute; low: release SENS output to CPU. System reset. Reset when low. Serial data input from CPU. Latch input from CPU. Serial data is latched at the falling edge. Serial data transfer clock input from CPU. GND. Sense input from SSP. Track jump count signal input. Serial data output to SSP. Serial data latch output to SSP. Latched at the falling edge. Serial data transfer clock output to SSP. Microcomputer extended interface (input A). Microcomputer extended interface (input B). Microcomputer extended interface (input C). Crystal selection input. Low for 16.9344MHz; high for 33.8688MHz Microcomputer extended interface (output). Focus OK input. Used for SENS output and the servo auto sequencer. Spindle motor on/off control output. Spindle motor servo control. Spindle motor servo control. GFS is sampled at 460Hz; when GFS is high, this pin outputs a high signal. If GFS is low eight consecutive samples, this pin outputs low. TEST pin. Normally GND. Master PLL (slave = digital PLL) filter output. Master PLL filter input. Master PLL charge pump output. Digital power supply for DSP. Analog GND for DSP. Master PLL VCO control voltage input.
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CXD2508AQ/AR
Pin No. R 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 Q 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68
Symbol AVDD1 RF BIAS ASYI ASYO ASYE WDCK LRCK LRCKI PCMD PCMDI BCK BCKI GTOP XUGF XPCK GFS RFCK VSS C2PO XROF MNT3 MNT1 MNT0 FSTT C4M DOUT EMPH EMPHI WFCK ZEROL ZEROR DTS1 VDD
I/O Analog power supply for DSP. I I I O I O O I O I O I O O O O O EFM signal input.
Description
Constant current input of asymmetry compensation circuit. Comparator voltage input of asymmetry compensation circuit. EFM full-swing output (low = Vss, high = VDD). Low: asymmetry compensation off; high: asymmetry compensation on. D/A interface for 48-bit slot. Word clock (2Fs). D/A interface for 48-bit slot. LR clock (Fs). LR clock input for DAC. (48-bit slot) D/A interface. Serial data (two's complement, MSB first). Audio data input for DAC. (48-bit slot) D/A interface. Bit clock. Bit clock input for DAC. (48-bit slot) GTOP output. XUGF output. XPLCK output. GFS output. RFCK output. GND.
O O O O O O O O O I O O O I
C2PO output. XRAOF output. MNT3 output. MNT1 output. MNT0 output. 2/3 frequency-divider output for Pins 73 and 74. 4.2336MHz output. Digital Out output. Outputs high signal when the playback disc has emphasis, low signal when no emphasis. DAC de-emphasis on/off. High: on; low: off. WFCK (write frame clock) output. No-sound data detection output; high when no sound data is detected. (Left channel) No-sound data detection output; high when no sound data is detected. (Right channel) Test pin 1 for DAC; normally low. Digital power supply for DAC.
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CXD2508AQ/AR
Pin No. R 67 68 69 70 71 72 73 74 75 76 77 78 Q 69 70 71 72 73 74 75 76 77 78 79 80
Symbol NLPWM LPWM AVDD2 AVDD3 XTAI XTAO AVSS3 AVSS2 NRPWM RPWM DTS2 DTS3
I/O O O
Description Left channel PWM output. (Reverse phase) Left channel PWM output. (Forward phase) Power supply for PWM driver. Power supply for crystal.
I O
33.8688MHz crystal oscillation circuit input. 33.8688MHz crystal oscillation circuit output. GND for crystal. GND for PWM driver.
O O I I
Right channel PWM output. (Reverse phase) Right channel PWM output. (Forward phase) DAC test pin 2; normally low. DAC test pin 3; normally low.
Note) * PCMD is an MSB first, two's complement output. * GTOP is used to monitor the frame sync protection status. (High: sync protection window released.) * XUGF is the negative pulse for the frame sync derived from the EFM signal. It is the signal before sync protection. * XPLCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge of XPLCK and the EFM signal transition point coincide. * GFS goes high when the frame sync and the insertion protection timing match. * RFCK is derived with the crystal accuracy. This signal has a cycle of 136. * C2PO represents the data error status. * XRAOF is generated when the 16K RAM exceeds the 4F jitter margin.
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CXD2508AQ/AR
Electrical Characteristics DC Characteristics Item
Output voltage (4) Output voltage (3) Output voltage (2) Output voltage (1) Input voltage (3) Input voltage (2) Input voltage (1)
(VDD = AVDD = 5.0V 5%, VSS = AVSS = 0V, Topr = -20 to +75C) NOTE) Conditions VIH (1) VIL (1) VIH (2) Schmitt input VIL (2) 0.8VDD 0.2VDD Min. 0.7VDD 0.3VDD Typ. Max. Unit V V V V Applicable pins 1
High level input voltage Low level input voltage High level input voltage Low level input voltage
2
Input voltage
VIN (3)
Analog input
VSS
VDD
V
3
High level output voltage Low level output voltage High level output voltage Low level output voltage High level output voltage Low level output voltage High level output voltage Low level output voltage
VOH (1) VOL (1) VOH (2) VOL (2) VOH (3) VOL (3) VOH (4) VOL (4) ILI ILO
IOH = -4mA IOL = 4mA IOH = -2mA IOL = 4mA IOH = -0.28mA IOL = 0.36mA IOH = -10mA IOL = 10mA VI = 0 to 5.25V VO = 0 to 5.25V
VDD-0.8 0 VDD-0.8 0 VDD-0.5 0 VDD-0.4 0
VDD 0.4 VDD 0.4 VDD 0.4 VDD 0.4 5 5
V V V V V V V V A A
4
5
6
7
Input leak current Tri-state pin output leak current
1, 2, 3 8
Applicable pins 1 XTSL, DATA, XLAT, PCMDI, EMPHI, DTS1, DTS2, DTS3, SPOA, SPOB, SPOC 2 CLOK, XRST, EXCK, SQCK, MUTE, FOK, SEIN, CNIN, ASYE, LRCKI, BCKI 3 CLTV, FILI, RF, BIAS, ASYI 4 MDP, PCO 5 ASYO, DOUT, FSTT, C4M, SBSO, SQSO, SCOR, EMPH, MON, LOCK, WDCK, DATO, CLKO, XLTO, SENS, MDS, LRCK, WFCK, PCMD, BCK, GTOP, XUGF, XPCK, GFS, RFCK, XROF, MNT0, MNT1, MNT3, ZEROL, ZEROR 6 FILO 7 LPWM, NLPWM, RPWM, NRPWM 8 SENS, MDS, MDP Note) "AVDD" refers to AVDD1, AVDD2, and AVDD3. In addition, "AVss" refers to AVss1, AVss2, and AVss3. -7-
CXD2508AQ/AR
AC Characteristics 1) XTAI pin (1) When using self-oscillation (Topr = -20 to +75C, VDD = AVDD = 5.0V 5%) Item Oscillation frequency Symbol fMAX Min. 15 Typ. Max. 34 Unit MHz
(2) When inputting pulses to XTAI (Topr = -20 to +75C, VDD = AVDD = 5.0V 5%) Item High level pulse width Low level pulse width Pulse cycle Input high level Input low level Rise time, fall time Symbol Min. 13 13 26 VDD - 1.0 0.8 10 Typ. Max. 500 500 1,000 Unit ns ns ns V V ns
tWHX tWLX tCK
VIHX VILX
tR, tF
tCX tWHX tWLX VIHX VIHX x 0.9
XTAI
VDD/2
VIHX x 0.1 VILX tr tr
(3) When inputting sine waves to XTAI via a capacitor (Topr = -20 to +75C, VDD = AVDD = 5.0V 5%) Item Input amplitude Symbol V1 Min. 2.0 Typ. Max. Unit
VDD + 0.3 Vp-p
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CXD2508AQ/AR
2) CLOK, DATA, XLAT, CNIN, SQCK EXCK pins (VDD = AVDD = 5.0V 5%, VSS = AVSS = 0V, Topr = -20 to +75C) Item Clock frequency Clock pulse width Setup time Hold time Delay time Latch pulse width EXCK SQCK frequency Symbol fCK Min. Typ. Max. 0.65 750 300 300 300 750 0.65 750
1/fCX tWCK CLK tWCK
Unit MHz ns ns ns ns ns MHz ns
tWCK tSU tH tD tWL
fT
EXCK SQCK pulse width fWT
DATA
XLT EXCK CNIN SQCK
tSU
tH
tD
tWL
tWT 1/fr SUBQ SQCK tSU tH
tWT
In pseudo double-speed playback mode, when SL0 = SL1 = 1, the maximum operating frequency for SQCK is 300kHz and the minimum pulse width is 1.5s. 3) BCKI, LRCKI, and PCMDI pins (VDD = AVDD = 5.0V 5%, VSS = AVSS = 0V, Topr = -20 to +75C) Item BCK pulse width DATAL, R setup time DATAL, R hold time LRCK setup time Symbol Conditions Min. 94 18 18 18
tW(BCKI) tW(BCKI) VDD/2 tH tSU (PCMDI) (PCMDI) VDD/2
Typ. 118
Max. 141
Unit nsec nsec nsec nsec
tW tSU tH tSU
BCKI
PCMDI tsu (LRCKI)
LRCKI
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CXD2508AQ/AR
1-bit DAC Block Analog Characteristics Item Total harmonic distortion S/N ratio Symbol THD Conditions 1kHz, 0dB data
(VDD = AVDD = 5.0V, VSS = AVSS = 0V, Ta = 25C) Playback mode Min. Typ. Max. 0.015 0.025 dB Unit %
Normal speed Pseudo double-speed playback
1kHz, Normal speed 87 0dB data 83 (using filter A) Pseudo double-speed playback For both items, Fs=44.1kHz The circuits for measuring the total harmonic distortion and S/N ratio are shown below. S/N
11k RPWM 470p 470p NRPWM 11k
4.7k 820p
4.7k
2700p 22 820p 4.7k 4.7k 560p 330k
SHIBASOKU (AM51A)
100
Audio Analyzer
4.7k 4.7k
Analog LPF Circuit
768Fs/384Fs (Normal speed/Pseudo double-speed playback) SHIBASOKU (AM51A) RPWM EFM Signal Generater RF CXD2508AQ/AR NRPWM NLPWM LPWM Analog Circuit Rch Lch A B Audio Analyzer
Block Diagram for Measuring Analog Characteristics
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CXD2508AQ/AR
Description of Functions 1. CPU Interface and Instructions * CPU interface This interface uses DATA, CLOK, and XLAT to set the modes. The interface timing chart is shown below.
750ns or more CLOK
DATA
D1
D2
D3
D0
D1
D2
D3 750ns or more
Data XLAT
Address
Registers 4 to E
Valid 300ns max
* Information on each address and the data is provided in Table 1-1. * The internal registers are initialized by a reset when XRST = 0; the initialization data is shown in Table 1-2. Note) When XLAT is low, EXCK and SQCK must be set high.
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Command Table
Data 1 Data 2 Data 3 D0 D2 -- -- -- -- -- -- D1 D3 D2 D1 -- -- D3 D0 D0 -- D0 AS0 -- -- -- -- -- -- -- 0.36ms 0.18ms 0.09ms 0.05ms 1 11.6ms 5.8ms 2.9ms 1.45ms 32768 16384 8192 2048 32 -- -- AD5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- AD4 -- -- -- -- -- -- -- -- -- AD6 0 DADS -- -- -- -- -- -- -- -- -- -- -- 0 -- -- -- -- -- -- -- -- -- -- -- -- 0 -- -- 1024 256 128 64 512 4096 CDROM 0 0 Mute 0 ATT SL 1 SL 0 CPUSR 0 DOUT DOUT WSEL MUTE ON/OFF DSPB 0 0 ON/OFF VCO SEL FSTT SEL 16 8 -- -- AD3 -- -- -- -- -- -- 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- D3 D2 D1 Data 4 D0 D3 D1 AS1 AS3 0.18ms 0.09ms 0.05ms 0.02ms 0 1 -- -- AS2 D2 0
Address D1 0
Register name
Command
D3
D2
4
Auto sequence
0
1
Blind (A, E), Overflow (C)
5
0
1
Brake (B)
6 1 1 0 1 0 1 0 1 0 CM3 CM1 CM0 Don't Use CM2 1 0 0 1 1 0 0 1 1
KICK (D)
0
1
7
Auto sequence (N) track jump count setting
0
1
4 -- -- AD2 -- -- -- -- --
2 -- -- AD1 -- -- -- -- --
1 -- -- AD0 -- -- -- -- --
8
MODE specification
1
0
9
Function specification
1
0
A
Audio CTRL
1
0
B
Serial bus CTRL
1
0
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Gain Gain Gain Gain MDP1 MDP0 MDS1 MDS0 CLVS DCLV TP Gain PWMmod TB
C
Servo coefficient setting
1
1
D
CLV CTRL
1
1
E
CLV mode
1
1
F
TEST mode
1
1
Table 1-1
CXD2508AQ/AR
Reset Initialization
Data 1 Data 2 Data 3 D0 D2 -- -- -- -- -- -- D1 D3 D2 D1 -- -- D3 D0 D0 -- D0 0 -- -- -- D3 D2 D1 Data 4 D0 D3 D1 0 0 0 D2 0
Address D1 0
Register name
Command
D3
D2
4 0 0 1 1 1 1 -- -- -- -- -- -- -- -- -- -- 0 1 0 -- -- -- -- -- -- -- 1 0 1 -- -- -- -- --
Auto sequence
0
1
Blind (A, E), Overflow (C) -- --
5
0
1
Brake (B)
6 1 0 0 0 1 0 1 1 1 0 0 -- -- -- 0 -- -- -- -- -- 0 -- -- -- -- 0 -- -- -- -- -- -- -- -- 0 -- -- -- -- -- 1 -- -- 1 -- -- -- -- -- 0 -- -- 0 0 0 -- 0 0 -- -- 1 -- -- -- -- -- 0 0 0 0 1 0 0 Don't Use -- -- -- -- -- 0 -- -- -- 1 -- -- -- -- -- 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 0 0 0 -- -- 1 -- -- -- -- --
KICK (D)
0
1
7
Auto sequence (N) track jump count setting
0
1
0 -- -- 1 -- -- -- -- --
0 -- -- 1 -- -- -- -- --
0 -- -- 1 -- -- -- -- --
8
MODE specification
1
0
9
Function specification
1
0
A
Audio CTRL
1
0
B
Serial bus CTRL
1
0
- 13 - Table 1-2
C
Servo coefficient setting
1
1
D
CLV CTRL
1
1
E
CLV mode
1
1
F
TEST mode
1
1
CXD2508AQ/AR
CXD2508AQ/AR
1-1. The meaning of the data for each address is explained below. $4X commands Command CANCEL FOCUS-ON 1 TRACK JUMP 10 TRACK JUMP 2N TRACK JUMP N TRACK MOVE AS3 0 0 1 1 1 1 AS2 0 1 0 0 1 1 AS1 0 1 0 1 0 1 RXF = 0 RXF = 0 AS0 0 1 RXF RXF RXF RXF FORWARD REVERSE
* When the FOCUS-ON command ($47) is canceled, $02 is sent and the auto sequence is interrupted. * When the TRACK JUMP/MOVE commands ($48 to $4F) are canceled, $25 is sent and the auto sequence is interrupted. $5X commands Auto sequence timer setting Setting timers: A, E, C, B Command Blind (A, E), Over flow (C) Brake (B) D3 0.18ms 0.36ms D2 0.09ms 0.18ms D1 0.05ms 0.09ms D0 0.02ms 0.05ms
Ex.) D2 = D0 = 1, D3 = D1 = 0 (Initial Reset) A = E = C = 0.11ms B = 0.23ms $6X commands Auto sequence timer setting Setting timer: D Command KICK (D) D3 11.6ms D2 5.8ms D1 2.9ms D0 1.45ms
Ex.) D3 = 0, D2 = D1 = D0 = 1 (Initial Reset) D = 10.15ms $7X commands Auto sequence TRACK JUMP/MOVE count setting (N) Command Data 1 Data 2 Data 3 Data 4
D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 Auto sequence track jump 15 14 13 12 11 10 2 2 2 2 2 2 number setting 29 28 27 26 25 24 23 22 21 20
This command is used to set N when a 2N TRACK JUMP and an N TRACK MOVE are executed for auto sequence. * The maximum track count is 65,535, but note that with 2N track jumps the maximum track jump count is determined by the mechanical limitations of the optical system. * The number of track jump is counted according to the signals input from CNIN pin. - 14 -
CXD2508AQ/AR
$8X commands Command MODE specification Data 1 D3 CDROM D2 DOUT MUTE D1 DOUT ON-OFF D0 WSEL D3 0 D2 0 Data 2 D1 0 D0 VCO SEL
Command bit CDROM = 1 CDROM = 0
C2PO timing 1-3 1-3
Processing CDROM mode; average value interpolation and pre-value hold are not performed. Audio mode; average value interpolation and pre-value hold are performed. Processing
Command bit DOUT MUTE = 1 DOUT MUTE = 0
Digital Out output is muted. (DA output is not muted.) When no other mute conditions are set, Digital Out output is not muted.
Command bit
Processing
DOUT ON-OFF = 1 Digital Out is output from the DOUT pin. DOUT ON-OFF = 0 Digital Out is not output from the DOUT pin.
Command bit WSEL = 1 WSEL = 0
Sync protection window width 26 channel clock 6 channel clock
Application Anti-rolling is enhanced. Sync window protection is enhanced.
In normal-speed playback, channel clock = 4.3218MHz. Command bit VCOSEL = 1 VCOSEL = 0 Processing VCO for double-speed playback is selected. VCO for normal-speed playback is selected. Application Double-speed playback or low voltage operation is possible. The selection is made for the normal speed playback.
$9X commands Command Function specifications Command bit DSPB = 0 DSPB = 1 Command bit FSTTSEL = 0 FSTTSEL = 1 The clock with two-thirds frequency of crystal is output to FSTT pin. The clock with the sixth frequency of crystal is output to FSTT pin. - 15 - Normal-speed playback Double-speed playback Data 1 D3 0 D2 DSPB ON-OFF D1 0 D0 0 D3 0 D2 0 Data 2 D1 0 D0 FSTT SEL
Processing
CXD2508AQ/AR
$AX commands Command Audio CTRL Data 1 D3 0 D2 0 D1 Mute D0 ATT D3 -- D2 -- Data 2 D1 DADS D0 --
Command bit Mute = 0 Mute = 1 Mute off.
Meaning
Command bit ATT = 0 ATT = 1
Meaning Attenuation off. -12dB
Mute on. 0 data is output from DSP. Processing Normal-speed playback for DAC block Double-speed playback for DAC block
Command bit DADS = 0 DADS = 1
In the case of using the crystal of 768Fs (Fs = 44.1kHz) Digital Attenuation The audio output level from DAC can be attenuated by setting AD6 to AC0 of register A. (with a built-in primary noise shaper) Command Audio CTRL Data 3 D2 AD6 D1 AD5 D0 AD4 D3 AD3 D2 AD2 Data 4 D1 AD1 D0 AD0
Command bit AD6 to AD0 7F (H) 7E (H) to 01 (H) 00 (H)
Audio output 0dB -0.13dB to -42.144dB -
The attenuation data consists of seven bits (AD6 to AC0), and 127 settings are possible. Audio output from 01 (H) to 7E (H) is determined according to the following formula: Audio output = 20 log ( attenuation data 128 ) dB
Ex.) When the attenuation data is 7A (H) Audio output=20 log ( 122 ) dB = -0.417dB 128
Soft Mute With soft mute function, when the attenuation data goes from 7F (H) (0dB) to 00 (H) (-) or vice versa, muting is turned on/off with a muting time of 1024/Fs [s] = 23.2 [ms] (Fs = 44.1kHz).
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CXD2508AQ/AR
Attenuation Operation Assume attenuation data X1, X2, and X3, where X1 > X3 > X2, and audio output Y1, Y2, and Y3, where Y1 > Y3 > Y2. First, assume X1 is transferred and then X2 is transferred. If X2 is transferred before Y1 is reached (state "A" in the diagram), then the value continues approaching Y2. Next, if X3 is transferred before Y2 is reached (either state "B" or "C" in the diagram), the value begins approaching Y3 from the current value at that point.
0dB 7F (H) A Y1 B Y3
C Y2 - 00(H)
23.2 [ms]
$BX commands Command Serial bus CTRL D3 SL1 D2 SL0 D1 CPUSR D0 0
This command switches the method of interfacing with the CPU. With the CDL500 series, the number of signal lines between the CPU and the DSP can be reduced in comparison with the CDL40 series. Also, the error rate can be measured with the CPU. Command bits SL1 0 0 1 1 SL0 0 1 0 1
Processing Same interface mode as the CDL40 series. SBSO is output from SQSO pin. In other words, subcodes P to W are read out from SQSO. Input the readout clock to SQCK. SENS is output from SQSO pin. Each output signal is output from SQSO pin. Input the readout clock to SQCK. (See the Timing Chart 1-2.)
Command bits CPUSR = 1 CPUSR = 0 XLON pin is high. XLON pin is low.
Processing
- 17 -
CXD2508AQ/AR
$CX commands Command Servo coefficient setting CLV CTRL ($DX) D3 Gain MDP1 D2 Gain MDP0 D1 Gain MDS1 D0 Gain MDS0 Gain CLVS
* CLVS mode gain setting: GCLVS Gain MDS1 0 0 0 0 1 1 Gain MDS0 0 0 1 1 0 0 Gain CLVS 0 1 0 1 0 1 GCLVS -12dB -6dB -6dB 0dB 0dB +6dB
* CLVP mode gain setting: GMDP, GMDS Gain MDP1 0 0 1 Gain MDP0 0 1 0 GMDP -6dB 0dB +6dB Gain MDS1 0 0 1 Gain MDS0 0 1 0 GMDS -6dB 0dB +6dB
- 18 -
CXD2508AQ/AR
$DX commands Command CLV CTRL D3 DCLV PWM MD D2 TB D1 TP D0 CLVS Gain See the $CX command.
Command bit DCLV PWM MD = 1 DCLV PWM MD = 0
Explanation (See the Timing Chart 1-3.) CLV PWM mode specified. Both MDS and MDP are used. CLV PWM mode specified. Ternary MDP values are output.
Command bit TB = 0 TB = 1 TP = 0 TP = 1
Explanation Bottom hold in CLVS mode at cycle of RFCK/32 Bottom hold in CLVS mode at cycle of RFCK/16 Peak hold in CLVS mode at cycle of RFCK/4 Peak hold in CLVS mode at cycle of RFCK/2
$EX commands Command CLV mode D3 CM3 D2 CM2 D1 CM1 D0 CM10
CM3 0 1 1 1 1 0 STOP KICK BRAKE CLVS CLVP CLVA
CM2 0 0 0 1 1 1
CM1 0 0 1 1 1 1
CM0 0 0 0 0 1 0
Mode STOP KICK BRAKE CLVS CLVP CLVA
Explanation See the Timing Chart 1-4. See the Timing Chart 1-5. See the Timing Chart 1-6.
: Spindle motor stop mode : Spindle motor forward rotation mode : Spindle motor reverse rotation mode : Rough servo mode. When RF-PLL circuit lock is disengaged, this mode is used to pull the disc rotations within the RF-PLL capture range. : PLL servo mode. : Automatic CLVS/CLVP switching mode. This mode is normally used during playback.
- 19 -
Timing Chart 1-1
LRCK
WDCK
CDROM = 0 Rch 16bit C1 Pointer Rch 16bit C2 Pointer If C2 Pointer = 1, data is NG
- 20 -
C2 Pointer for lower 8bits C2 Pointer for upper 8bits Rch C2 Pointer Lch C2 Pointer
C2P0
CDROM = 1 C2 Pointer for lower 8bits
C2P0
C2 Pointer for upper 8bits
CXD2508AQ/AR
Timing Chart 1-2
$BC latch
Set SQCK and EXCK high during this interval. 750ns or more (1500ns or more in low power consumption mode)
XLAT
Internal signal latch
SQCK
SQSO FOK LOCK RFCK
XRAOF
SPOA
SPOB SPOC XTSL WFCK SCOR GFS GTOP EMPH
C1F1 C1F2 C2F1
C2F2
- 21 - C1 correction status No Error Single error correction Irretrievable error C2F1 C2F2 0 1 1 0 0 1 C2 correction status No Error Single error correction Irretrievable error
CXD2508AQ/AR
C1F1 C1F2 0 0 1
0
1
1
CXD2508AQ/AR
Timing Chart 1-3
DCLV PWM MD = 0 MDS Z n * 236 (ns) n = 0 to 31 Acceleration MDP 132kHz 7.6s Deceleration Z
DCLV PWM MD = 0
MDS Acceleration Deceleration
MDP n * 236 (ns) n = 0 to 31
7.6s
Timing Chart 1-4
DCLV PWM MD = 0 STOP
MDS
Z
MDP
Z
MON
L
DCLV PWM MD = 1 STOP
MDS
MDP
L
MON
L
- 22 -
CXD2508AQ/AR
Timing Chart 1-5
DCLV PWM MD = 0 KICK MDS Z
MDP
H Z 7.6s
MON
H
DCLV PWM MD = 1 KICK
MDS
H
MDP
H
L MON H
- 23 -
CXD2508AQ/AR
Timing Chart 1-6
DCLV PWM MD = 0 BRAKE MDS Z
MDP
H
Z
MON
H
DCLV PWM MD = 1
MDS
MDP
MON
H
- 24 -
CXD2508AQ/AR
1-2. Description of SENS Output The following signals are output from SENS, depending on the microcomputer serial register value (latching not required). Microcomputer serial register SENS value (latching not required) output $0X, 1X, 2X, 3X $4X $5X $6X $AX $EX $7X, 8X, 9X, BX, CX, DX, FX SEIN Meaning SEIN, a signal input to the this IC from the SSP, is output.
XBUSY Low while the auto sequencer is in operation, high when operation terminates. FOK SEIN GFS OV64 "L" Outputs the signal input to the FOK pin. Normally, FOK (from RF) is input. High for "focus OK". SEIN, a signal input to this IC from the SSP, is output. High when the played back frame sync is obtained with the correct timing. Low when the EFM signal, after passing through the sync detection filter, is lengthened by 64 channel clock pulses or more. SENS pin is fixed low.
Note that the SENS output can be read from SQSO pin when SL1 = 1 and SL0 = 0. (See the $BX commands.) 2. Subcode Interface This section explains the subcode interface. There are two methods for reading out a subcode externally. The 8-bit subcodes P to W can be read from SBSO by inputting EXCK to the CXD2508AQ/AR. Sub Q can be read out after the CRC check of the 80 bits data in the subcode frame. This accomplished, after checking SCOR and CRCF, by inputting 80 clock pulses to SQCK and reading data from SQSO pin. 2-1. P to W Subcode Read Data can be read out by inputting EXCK immediately after WFCK falls. (See Fig. 2-1.) Also, SBSO can be read out from SQSO pin when SL1 = 0 and SL0 = 1. (See the $BX commands.) 2-2. 80-bit Sub Q Read Fig. 2-2 shows the peripheral block of the 80-bit Sub Q register. * First, Sub Q, regenerated at one bit per frame, is input to the 80-bit serial/parallel register and the CRC check circuit. * 96-bit Sub Q is input, and if the CRC is OK, it is output to SQSO with CRCF = 1. In addition, the 80 bits are loaded into the parallel/serial register. When SQSO goes high 400s or more later (monostable multivibrator time constant) after the subcode is read out, the CPU determines that new data (which passed the CRC check) has been loaded. * In the CXD2508AQ/AR, when 80-bit data is loaded, the order of the MSB and LSB is inverted for each byte. As a result, although the sequence of bytes is the same, the bits within the bytes are now ordered LSB first. * Once the fact that the 80-bit data has been loaded is confirmed, SQCK is input so that the data can be read. In the CXD2508AQ/AR, the SQCK input is detected, and when it is low the retriggerable monostable multivibrator is reset. * The retriggerable monostable multivibrator has a time constant from 270 to 400s. When the duration of SQCK is high is less than this time constant, the monostable multivibrator is kept reset; during this interval, the S/P register is not loaded into the P/S register. * While the monostable multivibrator is being reset, data can not be loaded in the 80-bit parallel/serial register. In other words, while reading out with a clock cycle shorter than the monostable multivibrator time constant, the register will not be rewritten by CRCOK and others. * Fig. 2-3 shows Timing Chart. * Although a clock is input from SQCK pin to actually perform these operations, the high and low intervals for this clock should be between 750ns and 120s. - 25 -
CXD2508AQ/AR
Timing Chart 2-1
Interrel PLL clock 4.3218 MHz
WFCK
SCOR
EXCK 400ns max SBSO S0 * S1 Q R
WFCK
SCOR
EXCK
SBSO
S0*S1 Q R S T U V W S0*S1
P1
Q R S T U V W P1
P2
P3
Same
Same Subcode P.Q.R.S.T.U.V.W Read Timing
- 26 -
Block Diagram 2-2
(AFRAM)
(ASEC)
(AMIN)
ADDRS CTRL
SUBQ 80bit S/P Register
SIN
ABCDEFGH
8 8 8 8 8 8 Order Inversion 8 8
8
HGFEDCBA 80bit S/P Register
SO
LD
LD
LD
LD
- 27 -
SUBQ
LD
LD
CRCC
Mono/Multi
SHIFT
LD
LD
SI
SHIFT
SQCK
CRCF SQSO Mix
CXD2508AQ/AR
Timing Chart 2-3
1 91 95 96 97 98 1 3 2 92 93 94
2 3
WFCK Order Inversion Determined by mode L 80 Clock CRCF2
SCOR
SQSO
CRCF1
SQCK Registere load forbidder
- 28 -
270 to 400s for SQCK = High 750ns to 120s ADR0 ADR1 ADR2 ADR3 CTL0 300ns max
Mono/multi (Interral)
SQCK
SQSO
CRCF
CTL1
CTL2
CTL3
CXD2508AQ/AR
CXD2508AQ/AR
3. Description of Other Functions 3-1. Channel Clock Regeneration by Digital PLL Circuit * The channel clock is necessary for demodulating the EFM signal regenerated by the optical system. Assuming T as the channel clock cycle, the EFM signal is demodulated in an integer multiple of T from 3T to 11T. In order to read the information in the EFM signal, this integer value must be read correctly. As a result, T, that is channel clock, is required. In an actual player, the fluctuation in the spindle rotation alters the width of the EFM signal pulses, making a PLL necessary for regenerating channel clock. The block diagram of this PLL is shown in Fig. 3-1. The CXD2508AQ/AR has a built-in two-stage PLL as shown in the diagram. * The first-stage PLL generates a high-frequency clock needed by the second-stage digital PLL. * The second-stage PLL is a digital PLL that regenerates the actual channel clock, and has a 250kHz (normal state) or more capture range. Block Diagram 3-1
OSC X'tal I/M Phase comparator PCO
I/N FILI
FILO
CLTV VCO
VDD
Digital PLL RFPLL
- 29 -
CXD2508AQ/AR
3-2. Frame Sync Protection * In a CD player operating at normal speed, a frame sync is recorded approximately every 136s (7.35kHz). This signal is used as a reference to know which data is the data within a frame. Conversely, if the frame sync can not be recognized, the data is processed as error data because it can not be recognized what the data is. As a result, recognizing the frame sync properly is extremely important for improving playability. * In the CXD2508AQ/AR, window protection and forward protection/backward protection have been adopted for frame sync protection. The adoption of these functions achieves very powerful frame sync protection. There are two window widths: one for cases where a rotational disturbance affects the player and the other for cases where there is no rotational disturbance (WSEL = 0/1). In addition, the forward protection counter is fixed to 13, and the backward protection counter is fixed to 3. In other words, when the frame sync is being played back normally and then can not be detected due to scratches, a maximum of 13 frames are inserted. If frame sync can not be detected for 13 frames or more, the window is released and the frame sync is resynchronized. In addition, immediately after the window is released and resynchronization is executed, if a proper frame sync can not be detected within 3 frames, the window is released immediately. 3-3. Error Correction * In the CD format, one 8-bit data contains two error correction codes, C1 and C2. For C1 correction, the code is created with 28-byte information and 4-byte C1 parity. For C2 correction, the code is created with 24-byte information and 4-byte parity. Both C1 and C2 are Reed-Solomon codes with a minimum distance of 5. * The CXD2508AQ/AR SEC strategy provides excellent playability through powerful frame sync protection and C1 and C2 error corrections. * The correction status can be monitored outside the LSI. See Table 3-1. * When the C2 pointer is high, the data in question was uncorrectable. Either the pre-value was held for that data, or an average value interpolation was made. MNT3 0 0 0 1 1 1 MNT1 0 0 1 0 0 1 MNT0 0 1 1 0 1 1 Description No C1 errors One C1 errors corrected C1 correction impossible No C2 errors One C2 errors corrected C2 correction impossible
Table 3-1.
- 30 -
CXD2508AQ/AR
Timing Chart 3-2
Normal-speed PB 400 to 500ns
RFCK
t = Dependent on error condition MNT3 C1 correction C2 correction
MNT1
MNT0
Strobe
Strobe
C4M
MNTO, 1, 3
Valid Invalid
Valid
3-4. DA Interface * The CXD2508AQ/AR DA interface is as described below. This interface includes 48 cycles of the bit clock within one LRCK cycle, and is MSB first. When LRCK is high, the data is for the left channel.
- 31 -
Timing Chart 3-3
48bit slot Normal-Speed Playback
LRCK (44.1k) 6 7 8 9 10 11 12 24
1
2
3
4
5
BCK (2.12M)
WDCK
PCMD L14 L13 L12 L11 L10 L9 L8 L7 L6
RO
Lch MSB (15)
L5
L4
L3
L2
L1
L0
RMSB
- 32 -
24 Rch MSB LO
48bit slot Double-Speed Playback
LRCK (88.2k)
1
2
BCK (4.23M)
WDCK
PCMD
Lch MSB (15)
RO
CXD2508AQ/AR
CXD2508AQ/AR
3-5. Digital Out There are three Digital Out formats: the type 1 format for broadcasting stations, the type 2 form 1 format for home use, and the type 2 form 2 format for the manufacture of software. The CXD2508AQ/AR supports type 2 form 1. Sub Q data which are matched twice in succession after a CRC check are input to the first four bits (bit 0 to 3) of channel status.
Digital Out C bit 0 0 ID0 16 0 1 2 3 4 0 5 0 6 0 7 0 8 1 9 0 10 0 11 0 12 0 13 0 14 0 15 0
From sub Q ID1 COPY Emph 0 0 0
0
0
0
0
0
0
0
0
0
0
0
0
32
48
0
176 bit0 to 3 - Sub Q control bits that matched twice with CRCOK
Table 3-2. 3-6. Servo Auto Sequencer This function performs a series of controls, including auto focus and track jumps. When the auto sequence command is received from the CPU, auto focus, 1 track jump, 2N track jumps, and N track move are executed automatically. SSP (servo signal processor LSI) is used in an exclusive manner during the auto sequence execution (when XBUSY = low), so that commands from the CPU are not transferred to the SSP, but they can be sent to the CXD2508AQ/AR. Connect the CPU, RF and SSP as shown in Fig. 3-4. When CLOK goes from low to high while XBUSY is low, XBUSY does not become high for a maximum of 100s after that point. This is designed to prevent the transfer of erroneous data to the SSP when XBUSY changes from low to high by the monostable multivibrator, which is reset by CLOK being low (when XBUSY is low).
- 33 -
CXD2508AQ/AR
(a) Auto Focus ($47) Focus search up is performed, FOK and FZC are checked, and the focus servo is turned on. If $47 is received from the CPU, the focus servo is turned on according to Fig. 3-5. The auto focus starts with focus search up, and the pickup should be lowered beforehand (focus search down). In addition, blind E of register 5 is used to eliminate FZC chattering. In other words, the focus servo is turned on at the falling edge of FZC after FZC has been continuously high for a longer time than E. Connection diagram for using auto sequencer (example)
RF FOK FOK
DATA CXD2508A C. out SSP SENS DATA CLK XLT CNIN SEIN DATO CLKO XLTO SENS CLOK Micro-computer XLAT
Fig. 3-4.
Auto focus
Focus search up
FOK = H YES
NO
(Checks whether FZC is continuously high or not for the period of time E set in register 5) FZC = H YES NO
FZC = L YES Focus servo ON
NO
END
Fig. 3-5-(a). Auto Focus Flow Chart - 34 -
CXD2508AQ/AR
$47latch
XLT
FOK
SEIN (FZC)
BUSY
Command for SSP $03
Blind E $08
Fig. 3-5-(b). Auto Focus Timing Chart (b) Track Jump 1, 10, and 2N-track jumps are performed respectively. Always use this when focus, tracking, and the sled servo are on. Note that tracking gain up and braking on ($17) should be sent beforehand because they are not performed. * 1-track jump When $48 ($49 for REV) is received from the CPU, an FWD (REV) 1-track jump is performed in accordance with Fig. 3-6. Set blind A and brake B with register 5. * 10-track jump When $4A ($4B for REV) is received from the CPU, an FWD (REV) 10-track jump is performed in accordance with Fig. 3-7. The principal difference between the 10-track jump and the 1-track jump is whether to kick the sled or not. In addition, after kicking the actuator, 5 tracks have been counted through CNIN, and the brake is applied to the actuator. Then, the actuator speed is found to have slowed up enough (determined by the CNIN cycle becoming longer than the overflow C set in register 5), and the tracking and sled servos are turned on. * 2N-track jump When $4C ($4D for REV) is received from the CPU, an FWD (REV) 2N-track jump is performed in accordance with Fig. 3-8. The track jump count "N" is set in register 7. Although N can be set to 216 tracks, note that the setting is actually limited by the actuator. CNIN is used for counting the number of jumps. Although the 2N-track jump basically follows the same sequence as the 10-track jump, the one difference is that after the tracking servo is turned on, the sled continues to move only for "D", set in register 6. * N-track move When $4E ($4F for REV) is received from the CPU, an FWD (REV) N-track move is performed in accordance with Fig. 3-9. N can be set to a maximum of 216 tracks. CNIN is used for counting the number of jumps. This N-track move uses a method in which only the sled is moved, and is suited for moves over thousands of tracks.
- 35 -
CXD2508AQ/AR
Track
Track kick sled servo WAIT (Blind A)
(REV kick for REV jump)
CNIN = NO YES Track REV kick WAIT (Brake B) Track sled servo ON (FWD kick for REV jump)
END
Fig. 3-6-(a). 1-Track Jump Flow Chart
$48 (REV = $49) latch
XLT
CNIN
BUSY
Command for SSP
Blind A $28 ($2C) $2C ($28)
Brake B $25
Fig. 3-6-(b). 1-Track Jump Timing Chart
- 36 -
CXD2508AQ/AR
10 Track
Track, sled FWD kick WAIT (Blind A) (Counts CNIN x 5)
CNIN=5 ? NO YES Track, REV kick
C = Overflow ? NO YES Track sled servo ON
(Checks whether the CNIN cycle is longer than overflow C)
END
Fig. 3-7-(a). 10-Track Jump Flow Chart
$4A (REV = $4B) latch
XLT
CNIN
BUSY
Blind A Command for SSP
CNIN 5count $2E ($2B)
Overflow C $25
$2A ($2F)
Fig. 3-7-(b). 10-Track Jump Timing Chart
- 37 -
CXD2508AQ/AR
2N Track
Track, sled FWD kick WAIT (Blind A)
CNIN = N NO YES Track REV kick
C = Overflow NO YES Track servo ON
WAIT (Kick D)
Sled servo ON
END
Fig. 3-8-(a). 2N-Track Jump Flow Chart
$4C (REV = $4D) latch
XLT
CNIN
BUSY
Blind A Command for SSP $2A ($2F)
CNIN N count $2E ($2B)
Overflow $26 ($27)
Kick D $25
Fig. 3-8-(b). 2N-Track Jump Timing Chart - 38 -
CXD2508AQ/AR
N Track move
Track servo OFF Sled FWD kick WAIT (Blind A)
CNIN = N NO YES Track, sled servo ON
END
Fig. 3-9-(a). N-Track Move Flow Chart
$4E (REV = $4F) latch
XLT
CNIN
BUSY
Blind A Command for SSP $22 ($23)
CNIN N count $25
Fig. 3-9-(b). N-Track Move Timing Chart
- 39 -
CXD2508AQ/AR
3-7. Digital CLV Fig. 3-10 shows the Block Diagram. Digital CLV makes PWM output in CLVS and CLVP with the MDS error and MDP error signal sampling frequency increased to 130kHz during normal-speed operation. In addition, the digital spindle servo can set the gain.
Digital CLV CLVS U/D MDS Error MDP Error
Gain
0, -6dB
Measure
Measure
CLVS P/S
2/1 MUX
Over Sampling Filter-1
GS (Gain) 1/2 Mux CLV P
GP (Gain)
CLV S
Over Sampling Filter-2
CLV-P/S
Noise Shape
KICK, BRAKE STOP
Modulation
Mode Select
MDP
DCLVMD
MDS
Fig. 3-10. Block Diagram
- 40 -
CXD2508AQ/AR
3-8. Asymmetry Compensation Fig. 3-11 shows the Block Diagram and Circuit Example.
ASYE
ASYO R1 RF R1
R2
R1 ASYI
R1
BIAS R2 2 = R1 5
Fig. 3-11. Example of Asymmetry Compensation Application Circuit
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
- 41 -
CXD2508AQ/AR
3-9. Setting Method of the CXD2508AQ/AR Playback Speed (a) Signal processing block (DSP block) The playback mode shown below can be selected by the combination of crystal, XTSL pin and doublespeed command (DSPB) in the CXD2508AQ/AR. Playback mode at DSP block Mode 1 2 3 4 51 Crystal 768Fs 768Fs 384Fs 384Fs 384Fs XTSL 1 1 0 0 1 DSPB 0 1 0 1 1 Speed at DSP block x1 x2 x1 x2 x1
Fs = 44.1kHz 1 Low power consumption mode. The processing speed is halved in the LSI so that the power consumption can be decreased. (b) DAC block The operating speed at DAC block is determined by the crystal and the double-speed command DADS in DAC block in spite of the operating conditions of DSP block mentioned above. Then, the playback mode for DAC block and DSP block can be determined independently. (For example, normal-speed playback for DSP block; low power consumption playback for DAC block.) The DAC block supports the normal speed and double speed. DADS is controlled by sending the command to DSP block. Playback mode at DAC block Mode 1 2 32 Crystal 768Fs 768Fs 384Fs DADS 0 1 1 Speed at DAC block x1 x2 x1
2 Low power consumption mode. The processing speed is halved in the LSI so that the power consumption can be decreased.
- 42 -
CXD2508AQ/AR
4. 1-bit DAC Block 4-1. PWM Output Pattern In the CXD2508AQ/AR, PWM outputs from the DAC include forward phase PWM (RPWM, LPWM) and inverted PWM (NRPWM, NLPWM). By determining the difference between these PWM outputs in the subsequent analog LPF, the noise and others can be canceled in the digital block. In addition, this method also yields improvements in the analog characteristics. The PWM output waveforms differ for each of the CXD2508AQ/AR three playback modes (normal, doublespeed, and pseudo double-speed). (In the following explanation, Fs = 44.1kHz.) During normal speed playback (DSPB = 0, crystal = 768Fs), eleven values (integers from -5 to 5) are taken within the 32Fs cycle. The minimum pulse width is -5, and the maximum pulse width is +5. The minimum variation width of change for PWM is the 384 Fs cycle. (See Fig. 4-3.)
LPWM (RPWM) Noise shaper output value NLPWM (NRPWM)
5
4
3***
* * * -3 -4 -5
-5 -4 -3 * * *
***3
4
5
33.8688 [MHZ] (768Fs)
1.4112 [MHZ] (32Fs)
Fig. 4-1. In double-speed playback (DSPB = 1, crystal = 768Fs), five values (-4, -2, 0, 2, 4) are taken within the 64Fs cycle. (See Fig. 4-4.)
4 LPWM (PRWM) -4 -2 2.8224 [MHz] (64Fs) 0 2 4 2 0 -2 -4 33.8688 [MHz] (768Fs)
Fig. 4-2. In pseudo double-speed playback (DSPB = 1, crystal = 384Fs), five values (-4, -2, 0, 2, 4) are taken within the 32Fs cycle. (See Fig. 4-5.)
4 LPWM (RPWM) -4 1.4112 [MHz] (32Fs) -2 0 2 4 2 0 -2 -4 16.9344 [MHz] (384Fs)
Fig. 4-3. 4-2. Input Timing for DAC Block Fig. 4-4 shows the input timing for DAC section. In the CXD2508AQ/AR, there is no internal transfer of sound data from the CD signal processing block to DAC block. Therefore, data can be transferred to DAC block through an audio DSP and others. When data is input to DAC block without passing through an audio DSP or similar device, data should be connected externally. In that case, EMPH, LRCK, and PCMD can be connected directly with EMPHI, LRCKI, and PCMDI respectively. (See the Application Circuit.) - 43 -
Normal-Speed Playback
LRCKI (44.1k) 6 7 8 9 10 11 12
1
2
3
4
5
24
BCKI (2.12M)
PCMDI RO L14 L13 L12 L11 L10 L9 L8 L7 L6 L5
Lch MSB (15)
L4
L3
L2
L1
L0
RMSB
- 44 -
24 Rch MSB
LO
Double-Speed Playback
LRCKI (88.2k)
1
2
BCKI (4.23M)
PCMDI
Lch MSB (15)
RO
CXD2508AQ/AR
Fig. 4-4. Input Timing for DAC Block
CXD2508AQ/AR
4-4. Description of Functions No-Sound Data Detection The no-sound data detection function detects low-level data on both the left and right channels in audio data from the 1Fs 48-bit slot and outputs a zero detection signal when that data continues unchanged for a certain period of time. The audio data is in two's complement format and data in which the upper 12 bits are all "0" or all "1" is regarded as low level data. When this data continues unchanged for 32,768 samples (743ms when Fs = 44.1kHz), the zero detection signal is output. In other words, once a certain period of time during which lowlevel data is detected elapses, the signal is regarded to be in the no-sound state. The zero detection signal is output from ZEROL (left channel) and ZEROR (right channel) pins. The zero detection output timing is shown in Fig. 4-5.
Lch LRCK 32,768th sample of low-level data 32,768th sample of low-level data Rch
ZEROR and ZEROL
Lch LRCK
Rch
Lch
Sound data
Rch
Lch
Rch
Lch
Rch
Lch
Low-level data Low-level data
Sound data Low-level data Low-level data Low-level data Low-level data Low-level data
ZEROL
ZEROR
Fig. 4-5. Zero Detection Output Timing
- 45 -
CXD2508AQ/AR
Forced Mute The forced mute can be executed independently for DSP block and DAC block. DSP can be forcibly muted by setting "1" in MUTE for D1 of register A. This mute can be released by setting "0" in MUTE for D1 of register A. Also, the both of left and right channels can be forcibly muted by inputting a high signal to MUTE pin for DAC block (in this event, a soft mute is not performed). In this instance, a fixed pattern is output for the PWM output. To release the mute, input a low signal to MUTE pin. Digital De-emphasis When EMPHI pin (Pin 63) is set high, de-emphasis can be applied by using the IIR filter. However, in normalplayback mode the time constants are as follows: 1 = 50s, 2 = 15s.
- 46 -
CXD2508AQ/AR
Application Circuit
GND
ZEROR
80 79 78
77 76 75 74 73 72 71 70 69 68 67 66 65
NLPWM
1 SCOR 2 SBSO 3 EXCK
NRPWM
ZEROR
ZEROL
WFCK 64 EMPHI 63 EMPH 62 DOUT 61 C4M 60 FSTT 59 MNT0 58 MNT1 57 MNT3 56 XROF 55 C2PO 54 XROF MNT0 MNT1 MNT2 MNT3 GND DOUT WFCK
4 SQSO 5 SQCK 6 MUTE LDON FOK SENS XRST DATA XLAT CLK GFS SQSO SQCK SCOR MUTE COUT VDD GND GND 7 SENS 8 XRST 9 DATA 10 XLAT 11 CLOK GND 12 Vss 13 SEIN 14 CNIN 15 DATO 16 XLTO 17 CLKO 18 SPOA 19 SPOB 20 SPOC 21 XTSL 22 XLON 23 FOK CXD2508AQ
RPWM
LPWM
AVDD3
AVDD2
AVss2
AVss3
DTS3
DTS2
DTS1
XTAI
XTA0
VDD
ZEROL
to CPU
Vss 53 RFCK 52 GFS 51 XPCK 50 XUGF 49 GTOP 48 BCKI 47 BCK 46 PCMDI 45 PCMD 44 LRCKI 43
RFCK GFS XPCK XUGF GTOP
AVDD1
AVSS1
LOCK
ASYO
TEST
CLTV
MDP
MDS
FILO
FILI
PCO
VDO
BIAS
ASYI
24 MON
ASYE
LRCK 42 WDCK 41 WDCK
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
GND
GND
RF
GND GND RF
LDON SSP
RF
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
DR IVER
- 47 -
GND
GND
to error rate counter
CXD2508AQ/AR
Package Outline CXD2508AQ
Unit: mm
80PIN QFP (PLASTIC)
23.9 0.4 + 0.4 20.0 - 0.1 64 41 + 0.1 0.15 - 0.05 0.15
65
40
+ 0.4 14.0 - 0.1
17.9 0.4
A 80 25 + 0.2 0.1 - 0.05
0.8
0.12
M
+ 0.15 0.35 - 0.1
+ 0.35 2.75 - 0.15
0 to 10 DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY RESIN SOLDER PLATING COPPER / 42 ALLOY 1.6g QFP-80P-L01 LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT
SONY CODE EIAJ CODE JEDEC CODE
QFP080-P-1420-A
CXD2508AQ
80PIN QFP (PLASTIC)
24.0 0.3 + 0.4 20.0 - 0.1 64 41
+ 0. 0.15 - 1 0.05
+ 0.4 14.0 - 0.1
18.0 0.3
0.7 0.
65
40
1
80
25
+ 0.2 0.1 - 0.05
1 0.8 0.12 M
24
+ 0.15 0.35 - 0.1
2.7 0.1 3.1 MAX
0 to 10 0.15
22.6
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-80P-L121 QFP080-P-1420-AX LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER PLATING 42 ALLOY 1.6g
- 48 -
16.6
0.8 0.2
1
24
16.3
CXD2508AQ/AR
CXD2508AQ
QFP 80PIN (PLASTIC)
23.9 0.2 20.0 0.2
0.15 0.05
64 65 41
40
14.0 0.2
17.9 0.2
0.8
80 1 0.35 0.1 0.15 M 24
15
25
4 - 1.0
A
15
C1
.2
4 - 0.8
1.45
15
0.8 0.15
0 to 10 DETAIL A
EPOXY RESIN SOLDER PLATING 42 ALLOY 1.6g
0.24 0.15 + 0.20 2.7 - 0.16
0.15
NOTE: Dimension "" does not include mold protrusion.
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-80P-L051 QFP080-P-1420-AH LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT
CXD2508AR
80PIN LQFP (PLASTIC)
14.0 0.2 60 61 12.0 0.1 41 40
2.94 0.15
15
A
80 1 0.5 0.08 + 0.08 0.18 - 0.03 20
21 (0.22)
+ 0.2 1.5 - 0.1
+ 0.05 0.127 - 0.02 0.1
0.1 0.1
0 to 10
0.5 0.2
NOTE: Dimension "" does not include mold protrusion.
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-80P-L01 QFP080-P-1212-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY / PHENOL RESIN SOLDER PLATING 42 ALLOY 0.5g
- 49 -
0.5 0.2
(13.0)
1.95 0.15

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